For a rich I/O interface on an integrated circuit, pin multiplexing is often required because the number of pins is limited. Several functions need to exist through one multiplexed interface.
FIG. 1 shows a known arrangement for pin multiplexing in a rich I/O interface. FIG. 1 shows a first core 101 and a second core 103, each linked to a shared I/O multiplexer 105. The two cores 101 and 103 together with the multiplexer 105 are located on a semiconductor chip. The shared I/O multiplexer 105 multiplexes between a set of shared pins 107.
In the arrangement described with reference to FIG. 1, the shared I/O multiplexer switches the multiplexed interface to the appropriate function at power up. That is, the I/O multiplexer selects the appropriate core 101 or 103 at start up. Thus, at any given time only one of the functions is working. Also, change to a different function is not possible without a restart and there are only limited choices for I/O functions to be multiplexed.